Avoid common noise coupling issues in layouts for high-current, fast-switching circuits.

Our 1ED44173/5/6 are the new low side gate driver ICs that integrate over-current protection (OCP), FAULT status output and enable function. This high integration level is excellent for the digitally controlled Power Factor Correction (PFC) applications with boost topology and ground reference switching.

In PFC applications, shunts are used to sense power switch current or DC bus current. The shunt’s location is different depending on the control methodology chosen. In figure 1, example 1, for example, the shunt is located between the IGBT emitter and system ground in order to sense the power switch’s current when the controller implements peak current control or current balance control in the interleaved PFC applications.

By contrast, figure 1, example 2 shows the shunt located between the system ground and negative DC bus minus rail in order to sense DC bus current. This configuration is popularly used in the average current mode control, and the digital controller can calculate input power based on average current and DC bus feedback.

Fig. 1: Two different types of low side gate drivers with OCP: 1ED44176N01F (Example 1) has positive current sense to meet the first shunt configuration, while 1ED44173/5N01B (Example 2) have the negative current sense to meet the second shunt configuration.

In today’s residential air conditioning (RAC) applications with digitally controlled PFC, the controller uses the power feedback signal to implement the adaptive DC bus voltage control. This allows lower losses at light loads when a lower DC bus is used and switches over to a full DC bus when a full load is required.

Because of the different shunt configurations, Infineon has designed two different types of the low side gate drivers with OCP: 1ED44176N01F (figure 1, example 1), as well as 1ED44173N01B and 1ED44175N01B (figure 1, example 2). The former has the positive current sense meet the first shunt configuration, while the latter two have the negative current sense meet the second shunt configuration. The 1ED44175N01B is targeted for use with IGBTs, while the 1ED44173N01B is targeted for use with MOSFETs.

Fig. 2: The table shows the differences between 1ED44173/5/6.

PCB layout is always a challenge in high-current, fast-switching circuits like PFC. A good PCB layout provides proper device operation and design robustness. Improper components or placement may cause erratic switching, excessive voltage ringing, or circuit latch-up.

The best PCB layout tips for gate driver ICs:

Let’s look at the effect the right layout can have. The following example shows the case of a circuit (figure 3) and layout implementation (figure 4) for the 1ED44175N01B and a TO-247 IGBT (e.g. IKW40N65WR5). With this design, it is possible to reduce the PCB trace loop area and inductance.

Fig. 3: Circuit diagram with 1ED44175N01B.

Fig. 4: Layout of the above circuit.

Factors leading to the reduction of PCB trace loop area and inductance:

Additionally, a ground plane connected to the COM helps as a radiated noise shield and provides some heat sinking for power dissipated within the device.

Following these layout tips eliminates common noise coupling issues which can cause mis-operation and reduce the initial design time.

Name* (Note: This name will be displayed publicly)

Email* (This will not be displayed publicly)

Suppliers are investing new 300mm capacity, but it’s probably not enough. And despite burgeoning 200mm demand, only Okmetic and new players in China are adding capacity.

Different interconnect standards and packaging options being readied for mass chiplet adoption.

Continued expansion in new and existing markets points to massive and sustained growth.

Experts at the Table: Designing for context, and geopolitical impacts on a global supply chain.

Funding rolls in for photonics and batteries; 88 startups raise $1.3B.

Disaggregation and the wind-down of Moore’s Law have changed everything.

It depends on whom you ask, but there are advantages to both.

Research shows significant improvement in time to market and optimization of key metrics.

Efficiency is improving significantly, but the amount of data is growing faster.

Some designs focus on power, while others focus on sustainable performance, cost, or flexibility. But choosing the best option for an application based on benchmarks is becoming more difficult.

The clock network is complex, critical to performance, but often it’s treated as an afterthought. Getting this wrong can ruin your chip.

Moving forward will require a fundamental reconsideration of logic.

After years of research, chipmakers have started combining ultra low-power designs with advancements in harvesting technology.